RTL Design Engineer

Responsibilities:

Develop RTL code for advanced ASIC designs.
Collaborate with architects and engineers to meet design specifications.
Optimize RTL code for area, power, and performance.
Conduct RTL simulations and assist with debugging.
Work with physical design teams for synthesis and timing closure.
Participate in design reviews and stay updated on industry trends.
Lead, supervise, coach, and mentor junior engineers.

Qualifications:

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
3+ years of experience in RTL design.
Proficiency in Verilog or VHDL.
Familiarity with EDA tools and design methodologies.
Strong problem-solving skills.
Excellent communication and teamwork.
Experience in Low Power Design (UPF) methodologies.
Experience in Synthesis, Constraint Development, Linting, CDC LEC, and STA.
Experience in scripting languages like Shell, Perl, Python, and PHP.
Knowledge of low-speed bus protocols (SPI/QSPI, I2C, I2S) and high-speed serial protocols (PCIe/USB/Ethernet).

Thanks & Regards
Pooja Karve
Talent Acquisition & HR
24th Main Sector-1,
HSR Layout, Bengaluru – 560102, Karnataka.